This invention relates generally to transistors and, more specifically, to a method for manufacturing transistors.
The demand for microprocessors to be made smaller is ever present because size reduction typically increases speed and decreases power consumption. Generally, making microprocessors smaller entails making the components of the microprocessors smaller. Transistors are one of the basic components of microprocessors. Thus, reducing the size of transistors enables microprocessors to be made smaller and, hence, have increased performance.
Transistors are typically manufactured by forming layers of material on top of one another with some type of processing being performed on each layer before depositing the next layer. Because some of the steps in the processing affect the entire device, at some stages of manufacturing, portions of the transistors must have inhibiting materials applied in order to at least retard the effects of certain later manufacturing steps. These inhibiting materials may often be applied to only inhibit the effects of a particular manufacturing step and, thus, may be of limited usefulness after they have served this purpose.
Unfortunately, once these limited purpose inhibiting materials have served their purpose, they may be difficult to remove. For example, since the components of transistors are typically quite small, on the order of a few to a few hundred nanometersxe2x80x9410xe2x88x929 meters, reducing the size of these materials by machining techniques is quite difficult, if not impossible. Moreover, because transistors are typically composed of a variety of materials, the application of an etchant to reduce the size of a particular material is problematic because the etchant tends to dissolve materials that do not require reduction.
The present invention provides a method that substantially reduces or eliminates at least some of the disadvantages and problems associated with previously developed methods for manufacturing transistors. Accordingly, in certain embodiments, the present invention provides a method that allows an inhibiting material on a transistor to be reduced while having a relatively small effect on the other materials of the transistor. Thus, the inhibiting material may be reduced after serving its primary purpose without significantly affecting the rest of the transistor, resulting in a smaller, yet operational transistor.
In accordance with the present invention, there is provided a transistor assembly including a silicon based semiconductor layer with a first surface. The assembly also includes a dielectric layer disposed on at least part of the first surface and a gate electrode disposed on the dielectric layer. The assembly farther includes an insulation layer adjacent at least part of the gate electrode and a nitride spacer layer adjacent at least part of the insulation layer. The method of the present invention includes depositing, on a portion of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer and depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the silicided portion of the first surface. The method additionally includes etch removing a portion of the pre-metal spacer layer above the silicided portion of the first surface to expose at least part of the silicided portion of the first surface and forming a contact with the exposed part of the silicided portion of the first surface where the pre-metal spacer layer was removed.
A transistor in accordance with the present invention includes a silicon based semiconductor layer having a first surface, at least a portion of the semiconductor layer adjacent the first surface having been silicided. The transistor also includes a dielectric layer disposed on at least part of the first surface and a gate electrode disposed on the dielectric layer. The transistor further includes an insulation layer adjacent at least part of the gate electrode and a nitride spacer layer adjacent at least part of the insulation layer. The distance from an edge of the gate electrode to the beginning of the silicided portion of the semiconductor layer is greater than the distance from the edge of the gate electrode to the edge of the nitride spacer layer closest the silicided portion.
The present invention allows the contacts of a transistor to be placed relatively close to the gate. This spacing allows the transistor to be made smaller, thereby providing increased speed and decreased power consumption in operation of the transistor, and any products into which it is incorporated, such as a microprocessor. Moreover, the present invention allows the transistor to be made smaller without significantly sacrificing performance characteristics of the transistor, such as current leakage between the source and the gate or the conductive characteristics of the semiconductor material. Thus, even though a transistor manufactured according to the present invention are smaller, at least certain performance characteristics may be comparable to those of larger transistors. The transistor may be made smaller through the use of standard manufacturing techniques, thereby allowing the transistor, and any resulting products into which it is incorporated, to be manufactured without a significant increase in cost over conventional transistors. Certain embodiments may possess none, one, some, or all of these technical features and advantages and/or additional technical features and advantages.
Other technical features and advantages will be readily apparent to one of skill in the art from the following figures, description, and claims.